کنفرانس مهندسی برق ایران

صفحه اصلی / سی و دومین کنفرانس بین المللی مهندسی برق

Low-Cost Clock Distribution Network in Highly Compact Integrated Circuits Against Single Event Transients

نویسندگان :

Ehsan Borhani nia¹ Amir Mohammad Hoseini²

1- دانشگاه صنعتی خواجه نصیرالدین طوسی 2- Faculty of Engineering Ferdowsi University of Mashhad, Mashhad, Iran

کلمات کلیدی :

Inverter،DIDO،Single event upsets،single event transient

چکیده :

With the advancement of technology and the shrinking dimensions of CMOS transistors, new challenges such as Clock Distribution Network (CDN) vulnerability to Single Event Transients (SET) have emerged. The clock signal is responsible for synchronizing information transfer in sequential circuits. The occurrence of SETs in CDN disrupts the timing of the transferred information, leading to errors in system performance. In this paper, a resilient clock distribution network against SETs is proposed. In order to fortify the clock distribution network against SETs, a Dual-Input Dual-Output (DIDO) inverter and a transient fault filter have been devised. The designed DIDO inverter extracts one of its outputs from PMOS transistors and the other from NMOS transistors. This design ensures that in the event of an error in one of the inverter outputs, its state is recovered by the other output and inputs. This mechanism prevents the propagation of errors throughout the entire clock distribution network.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 42.3.2