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صفحه اصلی
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سی و سومین کنفرانس بین المللی مهندسی برق
Designing a delay line independent of PVT (Process, Voltage, Temperature) and applying it to a TDC (Time to Digital Converter)
نویسندگان :
Sepehr Zare Teimoori
1
Mehdi Ehsanian
2
1- دانشگاه صنعتی خواجه نصیرالدین طوسی
2- دانشگاه صنعتی خواجه نصیرالدین طوسی
کلمات کلیدی :
Time to Digital Converter (TDC)،PVT Detector،Delay Line
چکیده :
In this research, a CMOS delay line in 0.18 μm technology with very low sensitivity to environmental effects (PVT) and high linearity is introduced and used as the input of an 8-bit Time-to-Digital Converter (TDC) with a Flash structure. The received delay resolution of this delay line is about 81 picoseconds and the resulting dynamic range is about 735 picoseconds. The measured delay changes without correction for the error introduced by PVT variations are about 73 picoseconds (approximately equal to the delay resolution), which is reduced to about 24 picoseconds after the PVT Detector circuit automatically detects and corrects the destructive PVT conditions. Also, the power consumption obtained from this design is 1.24 milliwatts.
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بیشتر
ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 43.6.0
