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صفحه اصلی
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سی و دومین کنفرانس بین المللی مهندسی برق
Multi-Bit Memory Architecture for In-memory Computing using In-Plane MTJ
نویسندگان :
Milad Ashtari Gargari
1
Nima Eslami
2
Mohammad Hossein Moaiyeri
3
1- دانشگاه شهید بهشتی
2- دانشگاه شهید بهشتی
3- دانشگاه شهید بهشتی
کلمات کلیدی :
In-memory computing (IMC)،spintronics،in-plane MTJ،magnetic logic
چکیده :
One promising solution to address the challenges faced by traditional Von Neumann architectures in dealing with big data is in-memory computing (IMC). Implementing IMC in memories leads to area overhead due to the design of sense amplifiers and required access transistors. One proposed method is using multi-bit cells to address the area-related challenges. This article presents a multi-bit cell capable of storing two bits and performing IMC. This architecture can execute all Boolean functions without external sense amplifiers. AND, NAND, NOR, and OR functions are implemented separately in a single cell. In addition, it can compute two functions simultaneously, such as AND with NOR (or NAND with OR). Transistor-level simulations using the HSPICE tool indicate a 99% improvement in energy consumption reduction compared to near-memory computing architectures. Additionally, a 60% and 65% improvement in energy consumption was achieved compared to state-of-the-art designs in implementing single and dual Boolean functions, respectively.
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بیشتر
ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 43.6.0
