کنفرانس مهندسی برق ایران

صفحه اصلی / سی امین کنفرانس بین المللی مهندسی برق

High Performance and Low Power Spintronic Binarized Neural Network Hardware Accelerator

نویسندگان :

Milad Tanavardi Nasab¹ Arefe Amirany² Mohammad Hossein Moaiyeri³ Kian Jafari⁴

1- دانشگاه شهید بهشتی 2- دانشگاه کاشان 3- دانشگاه شهید بهشتی 4- دانشگاه شهید بهشتی

کلمات کلیدی :

Binarized neural network hardware accelerator،CNTFET،Low power design،MTJ،XNOR-Net

چکیده :

Neural networks have shown a high ability to modeling and solve complex problems. Hardware implementation of neural network can also increase the efficiency of this system and in particular neural network hardware accelerators. In this paper, a high performance and low power spintronic binarized neural network hardware accelerator is proposed using nonvolatile feature of the magnetic tunnel junction (MTJ) and low leakage current of carbon nanotube field effect transistors (CNTFET). It is also noteworthy that the proposed design in this paper has the ability to implement the hardlimit activation function. Simulation results indicate the neural network implemented using the proposed design in this paper consumes 11% to 98% lower power, occupies 64% to 69% lower area, and offers 29% to 99% lower power delay area product (PDAP) than the state-of-the-art counterparts.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 42.8.0