کنفرانس مهندسی برق ایران

صفحه اصلی / بیست و نهمین کنفرانس مهندسی برق ایران

Design and Analysis of a Low-Power Two-Stage Dynamic Comparator with 40ps Delay in 65nm CMOS Technology

نویسندگان :

Razieh Ghasemi¹ Hossein Ghasemian² Ebrahim Abiri³ Mohammad Reza Salehi⁴

1- دانشگاه صنعتی شیراز 2- دانشگاه صنعتی شیراز 3- دانشگاه صنعتی شیراز 4- دانشگاه صنعتی شیراز

کلمات کلیدی :

Dynamic comparator, High speed, Delay time, Input-referred offset voltage, Two-stage comparator

چکیده :

A new high-speed low-power two-stage dynamic comparator is presented. In the first stage of the comparator, a positive feedback is used to reduce the delay time. Furthermore, in the reset phase, an NMOS switch is utilized between the differential output nodes of each stage to reduce the delay time. Moreover, the latch stage is activated with a predetermined delay to improve the offset voltage and the comparison speed. Furthermore, by using intermediate transistors between the first stage and the output latch, the delay time and offset voltage is improved. The equations related to the delay time and Input-referred offset voltage of the proposed structure are derived and the effective parameters to reduce them are identified. The post-layout simulation results in 65 nm CMOS technology demonstrate that the clock frequency of the proposed dynamic comparator can be 6 GHz while the delay time and standard deviation in offset voltage are 40 ps and 5.69 mV, respectively. The power consumption is 395.3 µW @ 6 GHz and 38 µW @ 1 GHz when the proposed comparator is supplied with 1.2 V. Also, the occupied area is 115.92 µm2 (12.6 µm× 9.2 µm).

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 42.5.3