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صفحه اصلی
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سی و دومین کنفرانس بین المللی مهندسی برق
A Low Phase Noise and High Frequency DLL-Based Clock Multiplier with Enhanced Locking Range
نویسندگان :
Alireza Toloue Khorasanian
1
Saeed Saeedi
2
1- دانشگاه تربیت مدرس تهران
2- دانشگاه تربیت مدرس
کلمات کلیدی :
Frequency synthesizer،Clock multiplier،delay-locked loop (DLL)،phase-locked loop (PLL)،Phase Noise
چکیده :
A low-phase noise, inductor less, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a hybrid topology is proposed for enhancing both phase noise and operation frequency. In this work, we employ a replica delay cell to preserve the phase information of the free-running VCO and a startup PLL circuit to increase the locking range. The proposed PLL topology uses the same loop as the ILCM topology, reducing the need for excessive chip area. Additionally, the CML divider of the PLL is disabled from the topology after the settling time of the PLL for power consumption reduction. The operation frequency enhancement can be achieved by using a TSPC flip-flop. With using this circuit, the operational frequency of the proposed hybrid topology is increased to 3.2 GHz, representing an improvement compared to similar works. The proposed hybrid topology was simulated using 65nm CMOS process. The output frequency is 3.2 GHz, with a phase noise of -119 dBc/Hz at a frequency offset of 100 KHz. The total power consumption is 9.6 mW.
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بیشتر
ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 44.7.2
