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صفحه اصلی
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بیست و نهمین کنفرانس مهندسی برق ایران
Hardware Implementation of a Chaos Based Image Encryption Using High-Level Synthesis
نویسندگان :
Saeed Sharifian.m.m
1
Vahid Rashtchi
2
Ali Azarpeyvand
3
1- دانشگاه زنجان
2- دانشگاه زنجان
3- دانشگاه زنجان
کلمات کلیدی :
Cryptography، Image Encryption، Chaos Theory، High-level Synthesis، FPGA
چکیده :
In recent years, the use of digital images in data transmission networks and digital devices has increased greatly. Therefore, the security of images in transmission or storage has become very important due to security attacks. For this reason, cryptography is used to protect images from unauthorized access and attacks. In this paper, an image encryption algorithm using chaos theory is proposed in which, besides providing the required level of security, the speed of encryption operations is also considered. Its security analyses have been performed by MATLAB software to check its efficiency in terms of security. Hardware implementation of the proposed algorithm has been done in FPGA, using high-level synthesis and architectural techniques, time and resource optimization. Based on our experimental results, the hardware designed for image encryption is robust in terms of security and it has low resource usage in the hardware. The proposed algorithm was able to achieve an encryption and decryption time of 21.14 milliseconds for an image with a size of 256×256.
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بیشتر
ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 43.6.0
