کنفرانس مهندسی برق ایران

صفحه اصلی / سی و یکمین کنفرانس بین المللی مهندسی برق

Low power SRAM using an optimal number of split bit lines and single-ended sensing

نویسندگان :

Mahdie Nazemian¹ Sayed Masoud Sayedi²

1- دانشگاه صنعتی اصفهان 2- دانشگاه صنعتی اصفهان

کلمات کلیدی :

(SRAM)Static Random Access Memory،Memory architecture،Low power memory،Sense amplifier،Divided bit lines،SKILL

چکیده :

In the proposed SRAM architecture in this work, the power is reduced by partitioning the structure into different blocks and also applying some power reduction techniques on the cells. The structure not only reduces power consumption but also increases the reading speed. For a read operation, by having an output line connected to the blocks, instead of the cells, it is possible for any given memory size to have an optimal number of blocks to decrease the power, without creating extra capacitive effects on the output lines. By reducing the power consumption in the inactive cells and reducing the capacitive load on the bit lines, both the power consumption and speed parameters have been improved . The memory structure is implemented by using the SKILL language to automatically implement any given memory size with an optimal number of blocks for minimum power consumption.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 41.7.4