کنفرانس مهندسی برق ایران

صفحه اصلی / سی امین کنفرانس بین المللی مهندسی برق

Area-Efficient Partially-Pipelined Architecture for Fast-SSC Decoding of Polar Codes

نویسندگان :

Mehdi Saeidi¹ Matin Hashemi²

1- دانشگاه صنعتی شریف 2- دانشگاه صنعتی شریف

کلمات کلیدی :

Polar Code،Hardware،Partially-Pipelined Architecture،Area Reduction

چکیده :

We propose a method to reduce the area of the state-of-the-art fully-unrolled partially-pipelined architecture for Fast Simplified Successive-Cancellation (Fast-SSC) decoding of polar codes. In state-of-the-art partially-pipelined architecture, compute units are idle during many of the clock cycles. The proposed solution alleviates some of this inefficiency. As a result, without degrading throughput or latency, area is reduced. For instance, compared to non-pipelined method, the proposed area-efficient partially-pipelined architecture reduces the area by a factor of 9.5x at initiation interval I = 20, while the state-of-the-art partially-pipelined architecture reduces the area by a factor of 7.4x. Hence, area efficiency is increased by a factor of about 1.28x in this case.

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بیشتر

ثمین همایش، سامانه مدیریت کنفرانس ها و جشنواره ها - نگارش 42.8.0