کنفرانس مهندسی برق ایران

صفحه اصلی / سی و چهارمین کنفرانس بین المللی مهندسی برق

High-Speed, ISI Noise-Free, Equalized Links in Interposer Excellency Using Augmented Stacked-Spiral; an Analytical Design Methodology

نویسندگان :

Ali Vatankhah¹ Nasser Masoumi²

1- دانشگاه تهران 2- دانشگاه تهران

کلمات کلیدی :

Silicon interposer،high-bandwidth memory (HBM)،high-speed serial link،inter-symbol interference (ISI)،transmission line،passive equalizer،stacked spiral inductor (SSI)

چکیده :

Heterogeneous integration with silicon interposers and high-bandwidth memories (HBM) face severe signal integrity challenges in high-speed chip-to-chip interconnects, where inter-symbol interference (ISI) is a dominant limitation. This paper presents a fully integrated passive equalizer implemented in a silicon interposer to mitigate ISI noise in redistribution-layer (RDL) links between stacked DRAM and system-on-chip (SoC) devices. The equalizer is composed of stacked spiral inductors (SSI), a metal–insulator–metal (MIM) capacitor, and two integrated resistors, forming a structure that provides high-frequency boosting. An analytical model based on transmission-line theory and ABCD matrices is developed to characterize the equalized transmission line. The proposed architecture achieves improved S21 flatness and significant bandwidth extension with acceptable DC attenuation, while remaining compact, area-efficient, and scalable for high-speed interposer-based serial links.